Implementation of the accelerated algorithms for integer division in the FPGA
DOI:
https://doi.org/10.18372/2073-4751.1.9261Abstract
The structural division of the implementation of the modules in the elemental basis of FPGA type FPGA, made by behavioral algorithms description language VHDL. Implemented check the functioning of the modules division simulation system ModelSim Xilinx Edition - MXE III with a test standReferences
Семенец В.В., Хаханова И.В., Xaханов В.И. Проектирование цифровых систем с использованием языка VHDL. - Харьков: ХНУРЕ, 2003. - 492 с.
Карцев М.А. Арифметика цифровых машин. - М: Наука, 1969. - 576 с.
VHDL'93. ШЕЕ Standard VHDL Language Reference Manual // IEEE Std 1076-1993.
Опанасенко B.H., Сахарин В.Г., Лисовый A.H. Проектирование модулей с плавающей точкой на ПЛИС с использованием языка VHDL. — К: Математические машины и системы. - №3 . 2005. - 195 с.
Downloads
How to Cite
Issue
Section
License
The scientific journal adheres to the principles of Open Access and provides free, immediate, and permanent access to all published materials without financial, technical, or legal barriers for readers.
All articles are published in Open Access under the Creative Commons Attribution 4.0 International (CC BY 4.0) license.
Copyright
Authors who publish their works in the journal:
-
retain the copyright to their publications;
-
grant the journal the right of first publication of the article;
-
agree to the distribution of their materials under the CC BY 4.0 license;
-
have the right to reuse, archive, and distribute their works (including in institutional and subject repositories), provided that proper reference is made to the original publication in the journal.
