Optimization of block of replacement of logical conditions in combined automation
DOI:
https://doi.org/10.18372/2073-4751.3.11315Keywords:
совмещенный автомат, FPGA, LUT, EMB, синтез, граф-схема алгоритмаAbstract
A method is proposed for synthesis of combined finite state machine. The method targets FPGAs. Itallows obtaining a circuit with minimum numbers of LUTs and EMBs. The optimization is achived dueto representing codes of pseudoequivalent states by generalized intervals of coding space. An exampleis given for application of proposed methodReferences
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