FPGA-based realization of generation algorithms pseudorandom words
DOI:
https://doi.org/10.18372/2410-7840.18.10848Keywords:
pseudorandom bit generator, simulation, CAD, DSP, FPGAAbstract
A hardware implementation of PSS generator based on FPGA crystals, which use the principle of reconfigurability that allows the modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning in this paper are proposed. Available embedded DSP blocks into structure of crystal FPGA allows efficient hardwarily implement the pseu-dorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level. With using of CAD ISE 14.02 Foundation by describing by means VHDL language implemented design and implementation on Spartan-based series crystal (6SLX4CSG225-3) for three types of the pseudorandom bit generators, for which time and hardware expenses are represented. With using the simulating system ModelSim SE 10.1c are obtained timing diagrams of simulation for these structures.References
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