Optimization of the circuit of combined automat IN BASIS NANO-PLA - Головін, Олександр Миколайович; Баркалов, Олександр Олександрович; Тітаренко, Лариса Олександрівна; Матвієнко, Олександр Володимирович; Сабурова, Світлана Олександрівна (Science-based technologies, 2020)
Nowadays, ASICs (application specific integrated circuit) are widely used for electronic products. One of the problems associated with this basis is to make smaller the area occupied by the circuit of the designed digital system. The solution to this problem allows to reduce the energy that the device circuit consumes, which is especially important for mobile and stand-alone devices. The aim of the work is to develop a method of synthesis that implements the scheme of a combined microprogramming machine (SMA) and allows one to reduce the number of horizontal buses of nano-PLA up to the value that is typical for an equivalent Moore finite state machine, and, as a result, to make smaller the area of ​​a nano-PLA, using the presence of classes of pseudo-equivalent states (PES) of a Mealy finite state machine . The article considers the example of an automaton synthesis using the proposed method. Based on the results of studies carried out with using standard examples from the well-known library, the proposed method allows one to make smaller the area of ​​the chip occupied by the automaton circuit by about three times. To achieve such savings, in a general case, it is necessary to jointly fulfill several conditions, namely: each PES class must be represented by one generalized interval of the state coding space, the minimum number of internal variables should be used for encoding the classes, and the state coding should be performed in such a way that each micro-operation was represented by only one term. Optimal coding of states makes it possible to reduce the number of rows in the table of transitions of the SMA and internal variables. The application of the proposed method, in comparison with the trivial two-level scheme, allows one to make smaller an area of ​​nano-PLA, which implements the SMA scheme in the ASIC basis.