About the Phase Noise of Frequency Synthesizers

Abstract

The paper proposes a variant of implementing a partial synthesizer with a small frequency step and preserving a sufficient level of phase noise in the X-band frequency range, which provides high frequency stability and low phase noise by combining 3 methods. A brief review of common methods for constructing frequency synthesizers, such as phase-locked loop, digital signal synthesis (DDS), dielectric resonator oscillator, is given. Their advantages and disadvantages were used and taken into account in the development of a new method for constructing a frequency synthesizer. The article compares the characteristics of the phase-locked loop frequency synthesizer on the ADF5355 chip with the developed method. The proposed method, which includes all 3 proposed methods, is presented in the form of a functional circuit containing two phase-locked loops and one DDS. The first PLL contains a dielectric resonator oscillator with an output signal of 8 GHz and a working frequency bandwidth of 1 kHz with a minimum phase noise equal to –132.85 dBc/Hz at a 1 kHz offset. The low-noise DDS signal is fed to the second phase-locked loop. The output signal is in the range of 9-9.5 GHz with a phase noise of –98.32 dBc/Hz at a 10 kHz offset.